MC908AP32CFBE Datasheet, PDF (252/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Analog-to-Digital Converter (ADC)
The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The
clock source is either the bus clock or CGMXCLK and is selectable by the ADICLK bit located in the ADC
clock register. The divide ratio is selected by the ADIV[2:0] bits.
For example, if a 4MHz CGMXCLK is selected as the ADC input clock source, with a divide-by-four
prescale, and the bus speed is set at 2MHz:
Conversion time =
16 to17 ADC cycles _{= 16 to 17 µs}
4MHz ÷ 4
Number of bus cycles = 16 µs × 2MHz = 32 to 34 cycles
NOTE
The ADC frequency must be between f_ADIC minimum and f_ADIC maximum
to meet A/D specifications. (See 22.5 5V DC Electrical Characteristics.).
Since an ADC cycle may be comprised of several bus cycles (four in the previous example) and the start
of a conversion is initiated by a bus cycle write to the ADSCR, from zero to four additional bus cycles may
occur before the start of the initial ADC cycle. This results in a fractional ADC cycle and is represented as
the 17th cycle.
15.3.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the selected channel, filling the ADC
data register with new data after each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit is set after each conversion and can be cleared by writing to the ADC status and control register
or reading of the ADRL0 data register.
15.3.5 Auto-Scan Mode
In auto-scan mode, the ADC input channel is selected by the value of the 2-bit up-counter, instead of the
channel select bits, ADCH[4:0]. The value of the counter also defines the data register ADRLx to be used
to store the conversion result. When ASCAN bit is set, a write to ADC status and control register (ADSCR)
will reset the auto-scan up-counter and ADC conversion will start on the channel 0 up to the channel
number defined by the integer value of AUTO[1:0]. After a channel conversion is completed, data is stored
in ADRLx and the COCO-bit will be set. The counter value will be incremented by 1 and a new conversion
will start. This process will continue until the counter value reaches the value of AUTO[1:0]. When this
happens, it indicates that the current channel is the last channel to be converted. Upon the completion on
the last channel, the counter value will not be incremented and no further conversion will be performed.
To start another auto-scan cycle, a write to ADSCR must be performed.
NOTE
The system only provides 8-bit data storage in auto-scan code, user must
clear MODE[1:0] bits to select 8-bit truncation mode before entering
auto-scan mode.
It is recommended that user should disable the auto-scan function before switching channel and also
before entering STOP mode.
MC68HC908AP Family Data Sheet, Rev. 4
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Freescale Semiconductor