MC908AP32CFBE Datasheet, PDF (256/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Analog-to-Digital Converter (ADC)
Table 15-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
Input Select
0
0
0
0
0
ADC0
PTA0
0
0
0
0
1
ADC1
PTA1
0
0
0
1
0
ADC2
PTA2
0
0
0
1
1
ADC3
PTA3
0
0
1
0
0
ADC4
PTA4
0
0
1
0
1
ADC5
PTA5
0
0
1
1
0
ADC6
PTA6
0
0
1
1
1
ADC7
PTA7
0
1
0
0
0
↓
↓
↓
↓
↓
1
1
1
0
0
ADC8
↓
ADC28
Reserved
1
1
1
0
1
ADC29
V_REFH (see Note 2)
1
1
1
1
0
ADC30
V_REFL (see Note 2)
1
1
1
1
1
ADC powered-off
—
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of
the ADC converter both in production test and for user applications.
15.7.2 ADC Clock Control Register
The ADC clock control register (ADICLK) selects the clock frequency for the ADC.
Address: $0058
Read:
0
0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
Write:
R
Reset: 0
0
0
0
0
1
0
0
= Unimplemented
R
= Reserved
Figure 15-4. ADC Clock Control Register (ADICLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
Table 15-2 shows the available clock configurations. The ADC clock should be set to between 500 kHz
and 1MHz.
MC68HC908AP Family Data Sheet, Rev. 4
254
Freescale Semiconductor