MC908AP32CFBE Datasheet, PDF (49/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option
register, MOR.
The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (2¹⁸ – 2⁴ or 2¹³ – 2⁴ ICLK cycles)
• Low-voltage inhibit (LVI) on V_DD
• LVI on V_REG
• LVI module reset
• LVI module in stop mode
• STOP instruction
• Stop mode recovery time (32 ICLK or 4096 ICLK cycles)
• Oscillator (internal, RC, and crystal) during stop mode
• Serial communications interface clock source (CGMXCLK or f_BUS)
The mask option register selects one of the following oscillator options:
• Internal oscillator
• RC oscillator
• Crystal oscillator
Addr.
Register Name
Bit 7
6
5
Configuration Register 2 Read: STOP_ STOP_ STOP_
$001D
(CONFIG2)^{† Write: ICLKDIS RCLKEN XCLKEN}
Reset: 0
0
0
$001F
Configuration Register 1 ^Read:
(CONFIG1)^†
Write:
Reset:
COPRS
0
LVISTOP LVIRSTD
0
0
$FFCF
Mask-Option-Register Read:
(MOR)^{# Write: OSCSEL1 OSCSEL0}
R
Erased: 1
1
1
† One-time writable register after each reset.
# _{MOR is a non-volatile FLASH register; write by programming.}
= Unimplemented
4
OSCCLK1
0
LVIPWRD
0
R
1
3
2
OSCCLK0
0
0
0
LVIREGD SSREC
0
0
R
R
1
1
R = Reserved
1
0
0
STOP
0
R
1
Bit 0
SCIBDSRC
0
COPD
0
R
1
Figure 3-1. CONFIG and MOR Registers Summary
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
49