MC908AP32CFBE Datasheet, PDF (263/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Port A
16.2 Port A
Port A is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter (ADC)
module. Port A pins also have LED direct drive capability.
16.2.1 Port A Data Register (PTA)
The port A data register contains a data latch for each of the eight port A pins.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTA7
Write:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by reset
Alternative Function: ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Additional Function: LED drive LED drive LED drive LED drive LED drive LED drive LED drive LED drive
Figure 16-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software-programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
ADC7–ADC0 — ADC Channels 7 to 0
ADC7–ADC0 are pins used for the input channels to the analog-to-digital converter module. The
channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used
as an ADC input and overrides any control from the port I/O logic.
NOTE
Care must be taken when reading port A while applying analog voltages to
ADC7–ADC0 pins. If the appropriate ADC channel is not enabled,
excessive current drain may occur if analog voltages are applied to the
PTAx/ADCx pin, while PTA is read as a digital input. Those ports not
selected as analog input channels are considered digital I/O ports.
LED drive — Direct LED drive pins
PTA7–PTA0 pins can be configured for direct LED drive. See 16.2.3 Port-A LED Control Register
(LEDA).
16.2.2 Data Direction Register (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
0
0
0
Figure 16-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
261