MC908AP32CFBE Datasheet, PDF (275/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

RESET
ACK2
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
PUC0ENB
IRQ2
V_DD
D ^CLR Q
CK
IRQ1 and IRQ2 Pins
SYNCHRONIZER
IMASK2
IRQ2F
IRQ2
INTERRUPT
REQUEST
MODE2
Figure 17-3. IRQ2 Block Diagram
17.4 IRQ1 and IRQ2 Pins
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK
bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that
poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK
bit another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program
counter with the vector address at location defined in Table 2-1 . Vector Addresses.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE
The BIH and BIL instructions do not read the logic level on the IRQ2 pin.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
273