MC908AP32CFBE Datasheet, PDF (60/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Central Processor Unit (CPU)
4.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary
Table 4-1 provides a summary of the M68HC08 instruction set.
4.8 Opcode Map
The opcode map is provided in Table 4-2.
Table 4-1. Instruction Set Summary
Source
Form
Operation
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AIS #opr
AIX #opr
Add with Carry
Add without Carry
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
Description
A ← (A) + (M) + (C)
A ← (A) + (M)
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
Effect on
CCR
VH I NZC
IMM
DIR
EXT
o
o
–
o
o
o
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
o
o
–
o
o
o
IX2
IX1
IX
SP1
SP2
– – – – – – IMM
– – – – – – IMM
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 4
E9 ff
3
F9
2
9EE9 ff
4
9ED9 ee ff 5
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 4
EB ff
3
FB
2
9EEB ff
4
9EDB ee ff 5
A7 ii
2
AF ii
2
MC68HC908AP Family Data Sheet, Rev. 4
60
Freescale Semiconductor