MC908AP32CFBE Datasheet, PDF (167/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Low-Power Modes
11.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
11.5.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to 7.6 Low-Power Modes for information on exiting wait mode.
11.5.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to 7.6 Low-Power Modes for information on exiting stop mode.
11.6 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
11.7 I/O Signals
Port B shares two of its pins with the SCI module.
The two SCI I/O pins are:
• PTB2/TxD — Transmit data
• PTB3/RxD — Receive data
11.7.1 TxD (Transmit Data)
When the SCI is enabled (ENSCI=1), the PTB2/TxD pin becomes the serial data output, TxD, from the
SCI transmitter regardless of the state of the DDRB2 bit in data direction register B (DDRB). The TxD pin
is an open-drain output and requires a pullup resistor to be connected for proper SCI operation.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
167