MC908AP32CFBE Datasheet, PDF (297/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Break Module Registers
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the break
;service routine software.
HIBYTE EQU
5
LOBYTE EQU
6
;
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN PULH
RTI
;Restore H register.
21.5.4 SIM Break Flag Control Register
The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while
the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset: 0
R
= Reserved
Figure 21-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
295