MC908AP32CFBE Datasheet, PDF (42/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Memory
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero
RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.5 FLASH Memory
This sub-section describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply. The program and erase operations are enabled
through the use of an internal charge pump. The following table shows the FLASH memory size and
address range:
Device
MC68HC908AP64
MC68HC908AP32
MC68HC908AP16
MC68HC908AP8
FLASH Size (Bytes)
62,368
32,768
16,384
8,192
Memory Address Range
$0860–$FBFF
$0860–$885F
$0860–$485F
$0860–$285F
2.5.1 Functional Description
The FLASH memory consists of an array for user memory plus a block of 48 bytes for user interrupt
vectors and one byte for the mask option register. An erased bit reads as logic 1 and a programmed bit
reads as a logic 0. The FLASH memory page size is defined as 512 bytes, and is the minimum size that
can be erased in a page erase operation. Program and erase operations are facilitated through control
bits in FLASH control register (FLCR). The address ranges for the FLASH memory are:
• $0860–$FBFF; user memory, 62,368 / 32,768 / 16,384 / 8,192 bytes
• $FFD0–$FFFF; user interrupt vectors, 48 bytes
• $FFCF; mask option register
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.⁽¹⁾
MC68HC908AP Family Data Sheet, Rev. 4
42
Freescale Semiconductor