MC908AP32CFBE Datasheet, PDF (302/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Electrical Specifications
Table 22-4. DC Electrical Characteristics (5V)
Characteristic⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Unit
Pullup resistors⁽⁹⁾
PTD[0:7]
RST, IRQ1, IRQ2
R_PU1
21
27
39
kΩ
R_PU2
21
27
39
kΩ
Low-voltage inhibit, trip falling voltage1⁽¹⁰⁾
V_TRIPF1
2.25
2.45
2.65
V
Low-voltage inhibit, trip rising voltage1⁽¹⁰⁾
V_TRIPR1
2.35
2.55
2.75
V
Low-voltage inhibit, trip voltage2⁽¹⁰⁾
V_TRIPF2
2.25
2.45
2.65
V
V_REG(10), ⁽¹¹⁾
V_REG
2.25
2.50
2.75
V
1. V_DD = 4.5 to 5.5 Vdc, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I_DD measured using external 32MHz clock to OSC1; all inputs 0.2 V from rail; no dc loads; less than 100pF
on all outputs; C_L = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects run I_DD; measured
with all modules enabled.
4. Wait I_DD measured using external 32MHz to OSC1; all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs.
C_L = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I_DD.
5. STOP I_DD measured using external 32.768kHz clock to OSC1; no port pins sourcing current.
6. STOP I_DD measured with OSC1 grounded; no port pins sourcing current.
7. Maximum is highest voltage that POR is guaranteed. The rearm voltage is triggered by V_REG.
8. If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V_DD is reached.
9. R_PU1 and R_PU2 are measured at V_DD = 5.0V
10. Values are not affected by operating V_DD; they are the same for 3V and 5V.
11. Measured from V_DD = V_TRIPF1 (Min) to 5.5 V.
22.6 5V Control Timing
Table 22-5. Control Timing (5V)
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Internal operating frequency⁽²⁾
f_OP
—
8
MHz
RST input pulse width low⁽³⁾
t_IRL
750
—
ns
1. V_DD = 4.5 to 5.5 Vdc, V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
formation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908AP Family Data Sheet, Rev. 4
300
Freescale Semiconductor