|
MC908AP32CFBE Datasheet, PDF (29/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. | |||
|
◁ |
Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes:
⢠62,368 bytes of user FLASH â MC68HC908AP64
32,768 bytes of user FLASH â MC68HC908AP32
16,384 bytes of user FLASH â MC68HC908AP16
8,192 bytes of user FLASH â MC68HC908AP8
⢠2,048 bytes of RAM â MC68HC908AP64 and MC68HC908AP32
1,024 bytes of RAM â MC68HC908AP16 and MC68HC908AP8
⢠48 bytes of user-defined vectors
⢠959 bytes of monitor ROM
2.2 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000â$005F. Additional I/O
registers have these addresses:
⢠$FE00; SIM break status register, SBSR
⢠$FE01; SIM reset status register, SRSR
⢠$FE02; Reserved
⢠$FE03; SIM break flag control register, SBFCR
⢠$FE04; interrupt status register 1, INT1
⢠$FE05; interrupt status register 2, INT2
⢠$FE06; interrupt status register 3, INT3
⢠$FE07; Reserved
⢠$FE08; FLASH control register, FLCR
⢠$FE09; FLASH block protect register, FLBPR
⢠$FE0A; Reserved
⢠$FE0B; Reserved
⢠$FE0C; Break address register high, BRKH
⢠$FE0D; Break address register low, BRKL
⢠$FE0E; Break status and control register, BRKSCR
⢠$FE0F; LVI Status register, LVISR
⢠$FFCF; Mask option register, MOR (FLASH register)
⢠$FFFF; COP control register, COPCTL
2.3 Monitor ROM
The 959 bytes at addresses $FC00â$FDFF and $FE10â$FFCE are reserved ROM addresses that
contain the instructions for the monitor functions. (See Chapter 8 Monitor ROM (MON).)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
29
|
▷ |