MC908AP32CFBE Datasheet, PDF (116/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Monitor ROM (MON)
RST
0.1 µF
V_DD
HC908AP
0.1 µF
V_{REG 4.9152MHz/9.8304MHz}
(50% DUTY)
OSC1
V_DD
V_DDA
V_REFH
V_REG
V_REFL
V_SS
V_SSA
CGMXFC
MUST BE USED IF SW2 IS AT POSITION C.
CONNECT TO OSC1, WITH OSC2 UNCONNECTED.
10 k
0.033 µF
0.01 µF
EXT OSC
4.9152 MHz
OSC1
1 µF
1 µF
DB9
2
3
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_CC ¹⁶
GND ¹⁵
2
V+
V– ⁶
10
9
6–30 pF
V_DD
+
1 µF
1 µF
+
XTAL CIRCUIT
V_TST
V_{DD 1 k}
1 µF
+
10 k
74HC125
6
5
74HC125
2
3
4
1M
6–30 pF
C
SW2 _{(SEE NOTE 1)}
8.5 V
D
V_DD
10 k
V_DD
V_DD
5
1
10 k
10 k
NOTES:
1. Monitor mode entry method:
SW2: Position C — High voltage entry (V_TST); must use external OSC
Bus clock depends on SW1 (note 2).
SW2: Position D — Reset vector must be blank ($FFFE:$FFFF = $FF)
Bus clock = 1.2288MHz.
2. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A — Bus clock = OSC1 4
SW1: Position B — Bus clock = OSC1 2
5. See Table 22-4 for V_TST voltage level requirements.
A
(SEE NOTE 2)
B
10 k
SW1
10 k
OSC2
IRQ1
PTA0
PTA1
PTB0
PTA2
Figure 8-1. Monitor Mode Circuit
MC68HC908AP Family Data Sheet, Rev. 4
116
Freescale Semiconductor