MC908AP32CFBE Datasheet, PDF (277/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

IRQ Registers
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
17.6.2 IRQ2 Status and Control Register
The IRQ2 status and control register (INTSCR2) controls and monitors operation of IRQ2. The INTSCR2
has the following functions:
• Enables/disables the internal pullup device on IRQ2 pin
• Shows the state of the IRQ2 flag
• Clears the IRQ2 latch
• Masks IRQ2 interrupt request
• Controls triggering sensitivity of the IRQ2 interrupt pin
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
PUC0ENB
Write:
0
IRQ2F
0
IMASK2 MODE2
ACK2
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 17-5. IRQ2 Status and Control Register (INTSCR2)
PUC0ENB — IRQ2 Pin Pullup Enable Bit.
Setting this bit to logic 1 disables the pullup on PTC0/IRQ2 pin.
Reset clears this bit.
1 = IRQ2 pin internal pullup is disabled
0 = IRQ2 pin internal pullup is enabled
IRQ2F — IRQ2 Flag Bit
This read-only status bit is high when the IRQ2 interrupt is pending.
1 = IRQ2 interrupt pending
0 = IRQ2 interrupt not pending
ACK2 — IRQ2 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ2 latch. ACK2 always reads as logic 0. Reset clears
ACK2.
IMASK2 — IRQ2 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ2 interrupt requests. Reset clears IMASK2.
1 = IRQ2 interrupt requests disabled
0 = IRQ2 interrupt requests enabled
MODE2 — IRQ2 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ2 pin. Reset clears MODE2.
1 = IRQ2 interrupt requests on falling edges and low levels
0 = IRQ2 interrupt requests on falling edges only
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
275