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MC908AP32CFBE Datasheet, PDF (289/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Chapter 20
Low-Voltage Inhibit (LVI)
20.1 Introduction
This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the
VDD pin and VREG pin, and can force a reset when VDD voltage falls below VTRIPF1, or VREG voltage falls
below VTRIPF2.
NOTE
The VREG pin is the output of the internal voltage regulator and is
guaranteed to meet operating specification as long as VDD is within the
MCU operating voltage.
The LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application VDD voltage collapsing completely to an unsafe level. It is not
intended that users operate the microcontroller at lower than the specified
operating voltage, VDD.
20.2 Features
Features of the LVI module include:
• Independent voltage monitoring circuits for VDD and VREG
• Independent disable for VDD and VREG LVI circuits
• Programmable LVI reset
• Programmable stop mode operation
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
$FE0F
LVI Status Register
(LVISR)
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-1. LVI I/O Register Summary
20.3 Functional Description
Figure 20-2 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains independent bandgap reference circuit and comparator for monitoring the VDD voltage and the
VREG voltage. An LVI reset performs a MCU internal reset and drives the RST pin low to provide
low-voltage protection to external peripheral devices.
LVISTOP, LVIPWRD, LVIRSTD, and LVIREGD are in the CONFIG1 register. See Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR) for details of the LVI configuration bits. Once
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
287