MC908AP32CFBE Datasheet, PDF (251/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

INTERNAL
DATA BUS
READ DDRAx
WRITE DDRAx
RESET
WRITE PTAx
READ PTAx
Functional Description
DDRAx
PTAx
DISABLE
ADC DATA REGISTERS
ADRH0 ADRL0
ADRL1
ADRL2
ADRL3
DISABLE
ADC0–ADC7
(8 CHANNELS)
PTAx/ADCx
VREFH
VREFL
INTERRUPT
LOGIC
CONVERSION
COMPLETE
10-BIT ADC
ADC
VOLTAGE IN
(V_ADIN)
CHANNEL
SELECT
AIEN COCO
CGMXCLK
BUS CLOCK
ADCICLK
CLOCK
GENERATOR
ADIV[2:0] ADICLK
MUX
ADCH[4:0]
ASCAN
2-BIT UP-COUNTER
AUTO[1:0]
Figure 15-2. ADC Block Diagram
15.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles, therefore:
Conversion time =
16 to17 ADC cycles
ADC frequency
Number of bus cycles = conversion time × bus frequency
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
249