MC908AP32CFBE Datasheet, PDF (35/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Monitor ROM
Addr.
Register Name
Bit 7
6
Read:
$0033
Timer 2 Channel 1 Status and
Control Register (T2SC1)
Write:
Reset:
CH1F
0
0
CH1IE
0
$0034
Timer 2 Channel 1 ^Read: _{Bit 15}
14
Register High Write:
(T2CH1H) _Reset:
$0035
Timer 2 Channel 1 ^Read: _{Bit 7}
6
Register Low Write:
(T2CH1L) _Reset:
Read:
PLLF
PLLIE
$0036 PLL Control Register (PCTL) Write:
Reset: 0
0
$0037
PLL Bandwidth Control Reg- ^Read:
ister Write:
(PBWC) _Reset:
AUTO
0
LOCK
0
PLL Multiplier Select ^Read:
0
0
$0038
Register High Write:
(PMSH) _Reset:
0
0
$0039
PLL Multiplier Select ^Read:
Register Low Write:
(PMSL) _Reset:
MUL7
0
MUL6
1
$003A
PLL VCO Range Select ^Read:
Register Write:
(PMRS) _Reset:
VRS7
0
VRS6
1
PLL Reference Divider ^Read:
0
0
$003B
Select Register Write:
(PMDS) _Reset:
0
0
Read:
$003C
Unimplemented Write:
Reset:
Read:
$003D
Unimplemented Write:
Reset:
Read:
$003E
Unimplemented Write:
Reset:
Read:
$003F
Unimplemented Write:
Reset:
U = Unaffected
X = Indeterminate
5
4
3
2
0
MS1A ELS1B ELS1A
0
0
0
0
13
12
11
10
Indeterminate after reset
5
4
3
2
Indeterminate after reset
PLLON
BCS
PRE1
PRE0
1
0
0
0
0
0
0
ACQ
0
0
0
0
0
0
MUL11 MUL10
0
0
0
0
MUL5
MUL4
MUL3
MUL2
0
0
0
0
VRS5
VRS4
VRS3
VRS2
0
0
0
0
0
0
RDS3
RDS2
0
0
0
0
1
TOV1
0
9
Bit 0
CH1MAX
0
Bit 8
1
Bit 0
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
35