MC908AP32CFBE Datasheet, PDF (109/324 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

7.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
Low-Power Modes
7.5.4 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting
its break interrupt output. (See Chapter 21 Break Module (BRK).) The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
7.5.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
7.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 7-15 shows
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if
the module is active or inactive in wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is logic 0, then the computer operating properly module (COP) is enabled and remains
active in wait mode.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
109