MCIMX27 Datasheet, PDF (942/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Fast Ethernet Controller (FEC)
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
29.3 Modes of Operation
The primary operational modes are described in this section.
29.3.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node to switch. Half
duplex mode is used in connections between an end node and a repeater or between repeaters. Selection
of the duplex mode is controlled by TCR[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE] and
TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and Section 29.5.10, “Full Duplex Flow Control,” for more
details.
29.3.2 Interface Options
The following interface options are supported. A detailed discussion of the interface configurations is
provided in Section 29.5.5, “Network Interface Options.”
29.3.2.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation.
The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE].
The speed of operation is determined by the FEC_TX_CLK and FEC_RX_CLK pins which are driven by
the external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by
software via the serial management interface (FEC_MDC/FEC_MDIO pins) to the transceiver. Refer to
the MMFR and MSCR register descriptions as well as the section on the MII for a description of how to
read and write registers in the transceiver via this interface.
29.3.2.2 10 Mpbs 7-Wire Interface Operation
The FEC supports a 7-wire interface as used by many 10 Mbps ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is deasserted, the MII mode is disabled and the
10 Mbps, 7-wire mode is enabled.
29.3.3 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),
and multicast hash match. Address recognition options are discussed in detail in Section 29.5.8, “Ethernet
Address Recognition.”
29-2
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor