MCIMX27 Datasheet, PDF (1371/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Single
Line
EAV
EAV_B
EAV_B
Blanking
Blanking
SOF
EAV_B
EAV_A
EAV_A
Blanking
Blanking
Blanking
SAV
SAV_B
SAV_B
Blanking
Blanking
SAV_B
SAV_A
SAV_A
Blanking
Data
Data
CMOS Sensor Interface (CSI)
Field 1
(F = 0)
EAV_A
Blanking
SAV_A
Data
4
Undefined
4
Configurable
Figure 39-5. CCIR656 Progressive Mode (General Case)
An interrupt is generated for SOF but not for COF. In the general case, when SOF information is retrieved
from the embedded coding, it is known as internal VSYNC mode. In other cases, when the VSYNC signal
is provided by the sensor, it is known as external VSYNC mode. The CSI can be operated in internal or
external VSYNC mode.
39.3.5 Error Correction for CCIR656 Coding
According to the algorithm for CCIR coding, protection bits in the SAV and EAV are encoded in the way
that allows a 1-bit error to be corrected, or a 2-bit error to be detected by the decoder. This feature is
supported by the CCIR decoder in CSI, for interlace mode only.
For the 1-bit error case, users can select the error to be corrected automatically, or simply shown as a status
flag instead. For the 2-bit error case, because the decoder is unable to make a correction, the error would
be shown as a status flag only.
An interrupt can be generated upon the detection of an error. This signal can be enabled or disabled without
affecting the operation of the status bit.
39.4 Interrupt Generation
This section describes CSI events that generate interrupts.
39.4.1 Start Of Frame Interrupt (SOF_INT)
The source of an SOF interrupt is dependent on the mode of operation.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
39-7