MCIMX27 Datasheet, PDF (1072/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

High-Speed USB On-The-Go (HS USB-OTG)
Table 30-51. qTD Token (DWord 2)
Bit
31
30:16
15
14:12
11:10
Description
Data Toggle. This is the data toggle sequence bit. The use of this bit depends
on the setting of the Data Toggle Control bit in the queue head.
Total Bytes to Transfer. This field specifies the total number of bytes to be
moved with this transfer descriptor. This field is decremented by the number of
bytes actually moved during the transaction, only on the successful completion
of the transaction. The maximum value software may store in this field is 5 * 4K
(5000H). This is the maximum number of bytes 5 page pointers can access. If
the value of this field is zero when the host controller fetches this transfer
descriptor (and the active bit is set), the host controller executes a zero-length
transaction and retires the transfer descriptor. It is not a requirement for OUT
transfers that Total Bytes To Transfer be an even multiple of QHD.Maximum
Packet Length. If software builds such a transfer descriptor for an OUT transfer,
the last transaction will always be less than QHD.Maximum Packet Length.
Although it is possible to create a transfer up to 20K this assumes the 1^st offset
into the first page is 0. When the offset cannot be predetermined, crossing past
the 5th page can be guaranteed by limiting the total bytes to 16K**. Therefore,
the maximum recommended transfer is 16K(4000H).
Interrupt On Complete (IOC). If this bit is set to a one, it specifies that when this
qTD is completed, the Host Controller should issue an interrupt at the next
interrupt threshold.
Current Page (C_Page). This field is used as an index into the qTD buffer
pointer list. Valid values are in the range 0H to 4H. The host controller is not
required to write this field back when the qTD is retired.
Error Counter (CERR). This field is a 2-bit down counter that keeps track of the
number of consecutive Errors detected while executing this qTD. If this field is
programmed with a non-zero value during set-up, the Host Controller
decrements the count and writes it back to the qTD if the transaction fails. If the
counter counts from one to zero, the Host Controller marks the qTD inactive,
sets the Halted bit to a one, and error status bit for the error that caused CERR
to decrement to zero. An interrupt will be generated if the USB Error Interrupt
Enable bit in the USBINTR register is set to a one. If HCD programs this field
to zero during set-up, the Host Controller will not count errors for this qTD and
there will be no limit on the retries of this qTD. Note that write-backs of
intermediate execution state are to the queue head overlay area, not the qTD.
Error Decrement Counter
Transaction Error Yes
Data Buffer Error No³
Stalled No¹
Babble Detected No¹
No Error No²
Error
Decrement Counter Error Decrement Counter
1 Detection of Babble or Stall automatically halts the queue head. Thus,
count is not decremented
30-90
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor