MCIMX27 Datasheet, PDF (803/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Keypad Port (KPP)
“1” to the appropriate bits in the KPCR. The lower 8 bits (7–0) are always in “totem pole” style, driven
when configured as outputs. See Table 25-1.
Table 25-1. Keypad Port Column Modes
KDDR
(15:8)
0
1
1
KPCR
(15:8)
x
0
1
Pin Function
Input
Totem-Pole Output
Open-Drain Output
NOTE
Totem pole capability should be provided for column pins. Totem pole
configuration helps for a faster discharge of keypad capacitance when all
columns need to be quickly brought to a “1” during the scan routine. With
this configuration, a time delay between the scanning of two subsequent
columns is reduced.
25.3 Memory Map and Register Definition
The KPP module contains four registers. Section 25.3.3, “Register Descriptions” provides detailed
descriptions of the KPP registers.
25.3.1 KPP Memory Map
Table 25-2 shows the KPP memory map.
Table 25-2. KPP Memory Map
Address
0x1000_8000 (KPCR)
0x1000_8002 (KPSR)
0x1000_8004 (KDDR)
0x1000_8006 (KPDR)
Use
Keypad Control Register
Keypad Status Register
Keypad Data Direction Register
Keypad Data Register
Access
R/W
R/W
R/W
R/W
Reset Value
0x0000
0x0000
0x0000
0x— — — —
Section/Page
25.3.3.1/25-5
25.3.3.2/25-5
25.3.3.3/25-7
25.3.3.4/25-8
25.3.2 Register Summary
Figure 25-2 shows the key to the register fields, and Table 25-3 shows the register figure conventions.
Always 1 Always 0 R/W BIT Read- BIT Write-
Write 1 BIT Self-clear 0 N/A
reads 1
reads 0
bit
only bit
only bit
to clear
BIT
w1c
bit
BIT
Figure 25-2. Key to Register Fields
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
25-3