MCIMX27 Datasheet, PDF (197/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions and Pin Assignments
Table 5-1. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
General Purpose Timers (X6)
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,
Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15.
TOUT1
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with
SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply
TOUT, and is also multiplexed with GPT6_TIN; PC14.
Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.
USB2.0
USBOTG_DIR/TXDM
USBOTG_STP/TXDM
USBOTG_NXT/TXDM
USBOTG_CLK/TXDM
USBOTG_DATA7/SUSPEND
USBH2_STP/TXDM
USBH2_NXT/TXDM
USBH2_DATA7/SUSPEND
USBH2_DIR/TXDM
USBH2_CLK/TXDM
USBOTG_DATA3/RXDP
USBOTG_DATA4/RXDM
USBOTG_DATA1/TXDP
USBOTG_DATA2/TXDm
USBOTG_DATA0/Oen
USBOTG_DATA6/SPEED
USBOTG_DATA5/RCV
USBH1_RXDP
USBH1_RXDM
USBH1_TXDP
USBH1_TXDM
USBH1_OE_B
USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2
USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1
USB OTG NEXT/Transmit Data Minus signal, multiplexed with KP_COL6A; PE0
USB OTG Clock/Transmit Data Minus signal, PE24
USB OTG Data7/Suspend signal, PE25
USB Host2 Stop signal/Transmit Data Minus signal, PA4
USB Host2 NEXT/Transmit Data Minus signal, PA3
USB Host2 Data7/Suspend signal, PA2
USB Host2 Direction/Transmit Data Minus signal, PA1
USB Host2 Clock/Transmit Data Minus signal; PA0
USB OTG data4/Receive Data Plus signal; multiplexed with SLCDC1_DAT15 through PC13
USB OTG data4/Receive Data Minus signal; multiplexed with SLCDC1_DAT14 through PC12
USB OTG data1/Transmit Data Plus signal; multiplexed with SLCDC1_DAT13 through PC11
USB OTG data2/Transmit Data Minus signal; multiplexed with SLCDC1_DAT12 through PC10
USB OTG data0/Output Enable signal; multiplexed with SLCDC1_DAT11 through PC9
USB OTG data6/Suspend signal; multiplexed with SLCDC1_DAT10 and USBG_TXR_INT_B
through PC8
USB OTG data5/RCV signal; multiplexed with SLCDC1_DAT9 through PC7
USB Host1 Receive Data Plus signal, multiplexed with UART4_RXD; multiplexed with
SLCDC1_DAT6 and UART4_RTS_ALT through PB31
USB Host1 Receive Data Minus signal; multiplexed with SLCDC1_DAT5 and UART4_CTS
through PB30
USB Host1 Transmit Data Plus signal; multiplexed with UART4_CTS, multiplexed with
SLCDC1_DAT4 and UART4_RXD_ALT through PB29
USB Host1 Transmit Data Minus signal; multiplexed with UART4_TXD, multiplexed with
SLCDC1_DAT3 through PB28
USB Host1 Output Enable signal; multiplexed with SLCDC1_DAT2 through PB27
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
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