MCIMX27 Datasheet, PDF (279/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Bootstrap Mode Operation
8.4.1 Bootstrap Protocol and Definition
In this section, bootstrap protocol and the command, response definition is defined. For the i.MX27
processor’s boot-up sequence, refer to System Boot. For the CSF, HW Configuration, Image definition,
refer to the High Assurance Boot (HAB).
8.4.1.1 Synchronization Operation
When bootstrap is firstly entered, the status of the iROM can be obtained by issuing the command shown
in Figure 8-2.
PC to i.MX27:
i.MX27 to PC:
SYNCH COMMAND
Figure 8-2. iROM Status Command
RESPONSE A
The SYNC COMMAND consists of 16 bytes using the format shown in Table 8-1.
:
Table 8-1. Synch Command Response Definition
Header
(2 bytes)
0505
Address
(4 bytes)
00000000
Format
(1 byte)
00
Bytecount
(4 bytes)
00000000
Data
(4 bytes)
00000000
End
(1 byte)
00
RESPONSE A is 4 bytes long using the format shown in Table 8-2.
Table 8-2. Response A Definition
Byte 0
STATUS CODE
Byte 1
STATUS CODE
Byte 2
STATUS CODE
Byte 3
STATUS CODe
8.4.1.2 Write Register Operation
To write to a register through bootstrap, requires a specific protocol. After the command is sent from PC
to MX27 processor, two responses are returned from MX27. One is used to indicate the type of silicon
(either HAB enable or disable), the other is used to indicate whether the write operation is successful.
PC to i.MX27:
i.MX27 to PC:
WRITE COMMAND
RESPONSE B
Figure 8-3. Write Register Command
RESPONSE C
WRITE COMMAND is 16 bytes long using the format shown in Table 8-3.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
8-3