MCIMX27 Datasheet, PDF (663/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

NF8BOOT or
NF16BOOT
NAND Flash Controller (NFC)
ipp_resetb
(POR)
NFC Operation
Sleep
hreset
Bootcode-copy done
BootCode-Copy
Idle
1)
ipi_int_nfc
2)
Figure 19-20. Boot Mode Operation
NOTE
2 Kbytes of bootcode copy takes about 160 µs. Host must read bootcode in
the RAM buffer (2 Kbytes) after bootcode copy completion.
Interrupt pin (ipi_int_nfc) goes from high to low when the bootcode-copy is
completed, and upon hreset rising edge. If hreset goes from Low to High
before bootcode-copy is done, Interrupt pin (ipi_int_nfc) goes from High to
Low as soon as bootcode-copy is completed.
The interrupt can be relevant for cases of secured boot (booting from ROM
and then enabling the NFC boot).
19.8.3 NAND Flash Control
NAND Flash Control generates all control signals that control the NAND Flash: CE (Flash Chip Enable),
RE (Read Enable for read operations), WE (Flash Write Enable), CLE (Flash Command Latch Enable),
ALE (Flash Address Latch Enable). It monitors R/nB (Flash Ready/Busy indication) signal to check if the
NAND Flash is in the middle of operation. BOOTLOADER is part of NAND Flash Control Block.
Figure 19-21, Figure 19-22, and Figure 19-23 show NAND Flash read, program, and erase timing
diagrams.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
19-21