MCIMX27 Datasheet, PDF (430/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Multi-Master Memory Interface (M3IF)
Table 16-14. MPG MAX Signals (continued)
AHB Master—Signal Name MPG—Signal Name
Description
S#_HBURST[2:0] (O)
S#_HADDR[31:0] (O)
S#_HWDATA[31:0] (O)
S#_HTRANS[1:0] (O)
S#_HBSTRB[3:0] (O)
S#_HUNALIGN (O)
S#_HMASTLOCK (O)
S#_HREADY (I)
M3IF_HBURST_M#[2:0] (I)
Burst information is provided using HBURST signal, and the 8
possible types are:
000 SINGLE (Single transfer)
001 INCR (Incrementing burst of unspecified length)
010 WRAP4 (4-beat wrapping burst)
011 INCR4 (4-beat incrementing burst)
100 WRAP8 (8-beat wrapping burst)
101 INCR8 (8-beat incrementing burst)
110 WRAP16 (16-beat wrapping burst)¹
111 INCR16 (16-beat incrementing burst)¹
M3IF_HADDR_M#[31:0] (I) Indicates the 32 bits memory ADDRESS bus.
M3IF_HWDATA_M#[31:0] (I)
The write data bus is driven by the master during write transfers
(on data phase). If the transfer is extended then the bus master
hold the data valid until the transfer completes, as indicated by
HREADY HIGH.
M3IF_HTRANS_M#[1:0] (I)
M3IF_HBSTRB_M#[3:0] (I)
Each transfer can be classified into one of four different types, as
indicated by the HTRANS[1:0] signals:
00 IDLE. Indicates that no data transfer is required. The IDLE
transfer type is used when a bus master is granted the bus,
but does not wish to perform a data transfer. M3IF will provide
a zero wait state OKAY response to IDLE transfers.
01 BUSY. BUSY transfer type allows bus masters to insert IDLE
cycles in the middle of bursts of transfers. This transfer type
indicates that the bus master is continuing with a burst of
transfers, but the next transfer cannot take place immediately.
M3IF will provide a zero wait state OKAY response to IDLE
transfers. When a master uses the BUSY transfer type the
address and control signals reflects the next transfer in the
burst.
10 NONSEQ. Indicates the first transfer of a burst or a single
transfer. Single transfers on the bus are treated as bursts of
one and therefore transfer type is NONSEQUENTIAL.
11 SEQ. The remaining transfers in a burst are SEQUENTIAL
and the address and control are related to the previous
transfer. In the case of a wrapping burst the address of the
transfer wraps at the boundary equal to the size (in bytes)
multiplied by the number of beats in the transfer (4,8 or 16).
Indicates which byte lanes are valid for each word transfer.²
M3IF_HUNALIGN (I)
Signal to indicate an unalign access requiring HBSTRB
information.²
M3IF_HMASTLOCK (I)
Indicates that the current master is performing a locked
sequence of transfers.
M3IF_HREADY_M# (O)
M3IF uses HREADY signal to insert the appropriate number of
wait states in to the transfer (the M3IF adds wait states as long
as the HREADY in signal is deasserted). The transfer completes
with HREADY HIGH (and an OKAY response, which indicates
the successful completion of the transfer). One wait state will be
added for every cycle that has HREADY diasserted.
16-20
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor