MCIMX27 Datasheet, PDF (1086/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

High-Speed USB On-The-Go (HS USB-OTG)
System software uses information in the host controller capability registers to determine how the ports are
routed to the companion host controllers. See Section HCSPARAMS—EHCI Compliant with extensions.¹
30.8.3.2.1 Port Routing Control via EHCI Configured (CF) Bit
Each port in the USB 2.0 host controller can be routed either to a single companion host controller or to
the EHCI host controller. The port routing logic is controlled by two mechanisms in the EHCI HC: a host
controller global flag and per-port control. The Configured Flag (CF) bit (defined in Section
BURSTSIZE), is used to globally set the policy of the routing logic. Each port register has a Port Owner
control bit which allows the EHCI Driver to explicitly control the routing of individual ports. Whenever
the CF bit transitions from a zero to a one (this transition is only available under program control) the port
routing unconditionally routes all of the port registers to the EHCI HC (all Port Owner bits go to zero).
While the CF-bit is a one, the EHCI Driver can control individual ports' routing via the Port Owner control
bit. Likewise, whenever the CF bit transitions from a one to a zero (as a result of Aux power application,
HCRESET, or software writing a zero to CF-bit), the port routing unconditionally routes all of the port
registers to the appropriate companion HC. The default value for the EHCI HC’s CF bit (after Aux power
application or HCRESET) is zero. Table 30-59 summarizes the default routing for all the ports, based on
the value of the EHCI HC’s CF bit.
The view of the port depends on the current owner. A Universal or Open companion host controller will
see port register bits consistent with the appropriate specification. Port bit definitions that are required for
EHCI host controllers are not visible to companion host controllers.
Table 30-59. Default Port Routing Depending on EHCI HC CF Bit
HS CF Bit
Default Port
Ownership
Explanation
0B
Companion
The companion host controllers own the ports and only Full-
HCs
and Low-speed devices are supported in the system. The
exact port assignments are implementation dependent. The
ports behave only as Full- and Low-speed ports in this
configuration
1B
EHCI HC
The EHCI host controller has default ownership over all of the
ports. The routing logic inhibits device connect events from
reaching the companion HCs' port status and control
registers when the port owner is the EHCI HC.The EHCI HC
has access to the additional port status and control bits
defined in this specification (see Section PORTSCx). The
EHCI HC can temporarily release control of the port to a
companion HC by setting the PortOwner bit in the PORTSC
register to a one.
30-104
1.If an implementation includes more than one set of companion and EHCI
host controllers, they are organized as groups of companion host controllers
with intermixed EHCI controllers.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor