MCIMX27 Datasheet, PDF (743/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Advanced Technology Attachment (ATA)
0x8000_1014 (TIME_CONFIG5)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
R
TIME_CYC
W
TIME_SS
Reset 0
0
0
0
0
0
0
1
0
0
0
0
0
0
17
16
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
R
TIME_CVH
W
TIME_DVS
Reset 0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 22-8. ATA TIME_CONFIG5 Register
Table 22-10. ATA TIME_CONFIG5 Register Field Descriptions
Field
Description
31–24 Ultra DMA mode time parameter counter for tCYC.
TIME_CYC
23–16 Ultra DMA mode time parameter counter for tSS.
TIME_SS
15–8
Ultra DMA mode time parameter counter for tCVH.
TIME_CVH
7–0
Ultra DMA mode time parameter counter for tDVS.
TIME_DVS
1
0
0
1
22.6.3.2 FIFO Data Registers
The FIFO_DATA register is used to read or write data to the internal FIFO. It can be accessed as a 16-bit
register or as a 32-bit register. Any long write to the register will put the four bytes written into the FIFO.
Any word write will put the two bytes written into the FIFO. Any long read will read four bytes from the
FIFO. Any word read will read two bytes from the FIFO.
22.6.3.2.1 FIFO_DATA_32 Register in 32-bit Mode
See Figure 22-9 for an illustration of valid bits in the FIFO_DATA_32 Register in 32-bit mode and
Table 22-11 for descriptions of the bit fields.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
22-15