MCIMX27 Datasheet, PDF (1431/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

enhanced Multimedia Accelerator Light (eMMA_lt)
0x1002_6008 (PP_INTRSTATUS)
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
R0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Figure 41-9. PP Interrupt Status Register
3
2
1
0
0
0 FRA
ERR
INTR
_EN
ME
COM
P
INTR
EN
0 w1c 0 w1c
Table 41-9. PP Interrupt Status Register Field Descriptions
Name
Description
31–3
Reserved. These bits are reserved and should be set to 0.
2
ERR_INTR
Error Interrupt Status. If set an error has occurred. The PP has to be reset (SWRST = 1)
before further operations can be initiated.
1
Reserved.
0
Frame Complete Interrupt Status. If set, a frame has been processed.
FRAME_COMP_INTR
41.4.4 PP Source Y Address Register
Figure 41-10 shows the register; Table 41-10 provides its field descriptions.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
41-17