MCIMX27 Datasheet, PDF (416/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Multi-Master Memory Interface (M3IF)
16.3 Memory Map and Register Definition
M3IF programming model consists of two classes of registers, M3IF control and lock registers and
snooping configuration and status registers as shown in Table 16-2. The control and master lock general
register defines the M3IF configurable logic functionality. The configuration and status registers set and
monitor snooping activity. All M3IF registers are 32-bits in length with bit fields defined in Figure 16-3
to Figure 16-10. All implemented bits are fully readable and writable in supervisor mode only (an error
response will be generated in case of user mode access to M3IF registers). All M3IF (and ESDCTL)
registers can be accessed only by a SINGLE word (32-bit) access, through the AHB bus protocol. Accesses
of any other size or type will cause an undetermined behavior.
All registers can be accessed by only one master at a time. Multi access to M3IF register causes
undetermined behavior. The only exception is M3IF Master Lock General register can be accessed by
more than one master at a time. The reset state of each bit is shown underneath the bit field name. An
asterisk indicates that the value is dependent on the operating mode selected during reset. Details are
provided in the following bit field descriptions.
16.3.1 Memory Map
M3IF supports four different memory controllers. Each memory controller defines a specific memory
address mapped as shown in Table 16-2. Table 16-3 shows the M3IF Memory Space Summary.
Table 16-2. M3IF Memory Map
Address
Register
0xD800_3000 (M3IFCTL) M3IF Control Register
0xD800_3028 (M3IFSCFG0) M3IF Snooping Configuration Register 0
0xD800_302C (M3IFSCFG1) M3IF Snooping Configuration Register 1
0xD800_3030 (M3IFSCFG2) M3IF Snooping Configuration Register 2
0xD800_3034 (M3IFSSR0) M3IF Snooping Status Register 0
0xD800_3038 (M3IFSSR1) M3IF Snooping Status Register 1
0xD800_3040 (M3IFMLWE0) M3IF Master Lock WEIM CS0 Register
0xD800_3044 (M3IFMLWE1) M3IF Master Lock WEIM CS1 Register
0xD800_3048 (M3IFMLWE2) M3IF Master Lock WEIM CS2 Register
0xD800_304C (M3IFMLWE3) M3IF Master Lock WEIM CS3 Register
0xD800_3050 (M3IFMLWE4) M3IF Master Lock WEIM CS4 Register
0xD800_3054 (M3IFMLWE5) M3IF Master Lock WEIM CS5 Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Section/Page
16.3.3.1/16-10
16.3.3.2/16-12
16.3.3.3/16-13
16.3.3.3/16-13
16.3.3.4/16-14
16.3.3.4/16-14
16.3.3.5/16-16
16.3.3.5/16-16
16.3.3.5/16-16
16.3.3.5/16-16
16.3.3.5/16-16
16.3.3.5/16-16
Table 16-3. M3IF Memory Space Summary
Address
Use
Access
0xA000_0000–0xAFFF_FFFF
ESDCTL/MDDRC Memory Space
CSD0 SDRAM or MDDR memory region (256 Mbyte) READ/WRITE
16-6
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor