MCIMX27 Datasheet, PDF (1027/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

High-Speed USB On-The-Go (HS USB-OTG)
Table 30-23. USBSTS Field Descriptions (continued)
Field
HCH
R
ULPII
R
SLI
SRI
URI
AAI
SEI
FRI
Description
HCHaIted — Read Only. 1=Default. This bit is a zero whenever the Run/Stop bit
is a one. The Host Controller sets this bit to one after it has stopped executing
because of the Run/Stop bit being set to 0, either by software or by the Host
Controller hardware (for example, internal error).
Only used by the host controller.
Reserved. These bits are reserved and should be set to zero.
ULPI Interrupt—R/WC. 0=Default. When the ULPI Viewport is present in the
design, an event completion will set this interrupt.
Used by both host and device controller. Only present in designs where
configuration constant VUSB_HS_PHY_ULPI = 1.
Reserved. These bits are reserved and should be set to zero.
DCSuspend—R/WC. 0=Default. When a device controller enters a suspend
state from an active state, this bit will be set to a one. The device controller clears
the bit upon exiting from a suspend state.
Only used by the device controller.
SOF Received—R/WC. 0=Default. When the device controller detects a Start Of
(micro) Frame, this bit will be set to a one. When a SOF is extremely late, the
device controller will automatically set this bit to indicate that an SOF was
expected. Therefore, this bit will be set roughly every 1ms in device FS mode and
every 125ms in HS mode and will be synchronized to the actual SOF that is
received.
Since the device controller is initialized to FS before connect, this bit will be set
at an interval of 1ms during the prelude to connect and chirp.
In host mode, this bit will be set every 125us and can be used by host controller
driver as a time base.
Software writes a 1 to this bit to clear it.
This is a non-EHCI status bit.
USB Reset Received—R/WC. 0=Default. When the device controller detects a
USB Reset and enters the default state, this bit will be set to a one. Software can
write a 1 to this bit to clear the USB Reset Received status bit.
Only used by the device controller.
Interrupt on Async Advance — R/WC. 0=Default. System software can force the
host controller to issue an interrupt the next time the host controller advances the
asynchronous schedule by writing a one to the Interrupt on Async Advance
Doorbell bit in the USBCMD register. This status bit indicates the assertion of
that interrupt source.
Only used by the host controller.
System Error— R/WC. This bit is not used in this implementation and will always
be set to “0”.
Frame List Rollover — R/WC. The Host Controller sets this bit to a one when the
Frame List Index rolls over from its maximum value to zero. The exact value at
which the rollover occurs depends on the frame list size. For example. If the
frame list size (as programmed in the Frame List Size field of the USBCMD
register) is 1024, the Frame Index Register rolls over every time FRINDEX [1 3]
toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every
time FHINDEX [12] toggles.
Only used by the host controller.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
30-45