MCIMX27 Datasheet, PDF (1061/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

High-Speed USB On-The-Go (HS USB-OTG)
Figure 30-45. Asynchronous Schedule Organization
The Asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply
pointer to the next queue head. This implements a pure round-robin service for all queue heads linked into
the asynchronous list.
30.8.2.3 Isochronous (High-Speed) Transfer Descriptor (iTD)
The format of an isochronous transfer descriptor is illustrated in Table 30-36. This structure is used only
for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous
TDs must be aligned on a 32-byte boundary.
Table 30-36. Isochronous Transfer Descriptor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Next Link Pointer
0 Typ T 03-0
Status
Transaction 0 Length
io PG*
Transaction 0 Offset*
07-0
Status
Transaction 1 Length
io PG*
Transaction 1 Offset*
0B-0
Status
Transaction 2 Length
io PG*
Transaction 2 Offset*
0F-0
Status
Transaction 3 Length
io PG*
Transaction 3 Offset*
13-1
Status
Transaction 4 Length
io PG*
Transaction 4 Offset*
17-1
Status
Transaction 5 Length
io PG*
Transaction 5 Offset*
1B-1
Status
Transaction 6 Length
io PG*
Transaction 6 Offset*
1F-1
Status
Transaction 7 Length
io PG*
Transaction 7 Offset*
23-2
Buffer Pointer (Page 0)
EndPt R Device Address 27-2
Buffer Pointer (Page 1)
I/ Maximum Packet Size 2B-2
Buffer Pointer (Page 2)
Reserved
Mult 2F-2
Buffer Pointer (Page 3)
Reserved
33-3
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
30-79