MCIMX27 Datasheet, PDF (1548/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Synchronous Serial Interface (SSI)
Table 42-19. SSI FIFO Control/Status Register Field Descriptions (continued)
Field
Description
19–16
TFWM1[3:0]
Transmit FIFO Empty WaterMark 1. These bits control the threshold at which the TFE1 flag will be set.
The TFE1 flag is set whenever the data level in Tx FIFO 1 falls below the selected threshold. Settings for
transmit FIFO watermark bits:
0000 Reserved
0001 TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default)
Transmit FIFO empty is set when TxFIFO <= 7 data.
0010 TFE set when there are more than or equal to 2 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO <= 6 data.
0011 TFE set when there are more than or equal to 3 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO <= 5 data.
0100 TFE set when there are more than or equal to 4 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO <= 4 data.
0101 TFE set when there are more than or equal to 5 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO <= 3 data.
0110 TFE set when there are more than or equal to 6 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO <= 2 data.
0111 TFE set when there are more than or equal to 7 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO <= 1 data.
1000 TFE set when there are 8 empty slots in Transmit FIFO.
Transmit FIFO empty is set when TxFIFO=0 data.
15–12
Receive FIFO Counter 0. These bits indicate the number of data words in Receive FIFO 0.
RFCNT0[3:0]
11–8
Transmit FIFO Counter 0. These bits indicate the number of data words in Transmit FIFO 0.
TFCNT0[3:0]
7–4
Receive FIFO Full WaterMark 0. These bits control the threshold at which the RFF0 flag will be set. The
RFWM0[3:0] RFF0 flag is set whenever the data level in Rx FIFO 0 reaches the selected threshold.
3–0
Transmit FIFO Empty WaterMark 0. These bits control the threshold at which the TFE0 flag will be set.
TFWM0[3:0] The TFE0 flag is set whenever the data level in Tx FIFO 0 falls below the selected threshold.
Table 42-20 indicates the status of the Transmit FIFO empty flag, with different settings of the Transmit
FIFO WaterMark bits and varying amounts of data in the Tx FIFO.
Table 42-20. Status of Transmit FIFO Empty Flag
Transmit FIFO
Number of data in TXFIFO
Watermark (TFWM) _{0 1 2 3 4 5 6 7 8}
1
111111110
2
111111100
3
111111000
4
111110000
5
111100000
6
111000000
7
111000000
8
100000000
42-54
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor