MCIMX27 Datasheet, PDF (126/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Clocks, Power Management, and Reset Control
4. Wait at least 30.5 us (1 cycle of 32 kHz clock) for system to update OSC26M_PEAK bits.
5. Repeat steps 2 to 4 until trimmed in desired range.
6. Decrement 4 additional counts to provide a margin of error for temperature drift.
7. Store trim value in an external memory—that is, Flash, for future use.
It is suggested that the proceeding algorithm be run to determine the optimum AGC setting. Once this is
done on power-up or system reset the software must read the trim value from the external memory and
write it to the OSC26M_AGC[5:0].
3.4.9 Peripheral Clock Divider Register 0 (PCDR0)
The Peripheral Clock Divider Register 0 (PCDR0) contains the divider values for the peripheral clock
dividers in the PLL Clock Controller. Peripherals in the i.MX27 device require special clock frequency
which is divided down from the MPLL and the SPLL clock output. Each of these peripheral modules
receive their clock input from the respective clock divider. These modules will still have the clock gating
scheme as with other modules for power saving advantages.
Figure 3-10 shows the register and Table 3-14 provides the field descriptions.
Table 3-16 lists the clock sources associated with the i.MX27 peripherals given in the PCDR0.
0x1002_7018 (PCDR0)
Access: User R/W
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
SSI2DIV
CLKO
_EN
CLKO_DIV
SSI1DIV
Reset 0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
H264DIV
W
NFCDIV
MSHCDIV
Reset 0
0
0
1
0
1
0
0
1
1
0
0
0
0
1
1
Figure 3-10. Peripheral Clock Divider Register 0 (PCDR0)
3-20
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor