MCIMX27 Datasheet, PDF (1181/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

High-Speed USB On-The-Go (HS USB-OTG)
Resume
If the device controller is suspended, its operation is resumed when any non-idle signaling is received on
its upstream facing port. In addition, the device can signal the system to resume operation by forcing
resume signaling to the upstream port. Resume signaling is sent upstream by writing a ‘1’ to the Resume
bit in the in the PORTSCx while the device is in suspend state. Sending resume signal to an upstream port
should cause the host to issue resume signaling and bring the suspended bus segment (one more devices)
back to the active condition.
Note: Before resume signaling can be used, the host must enable it by using the
Set Feature command defined in device framework (chapter 9) of the USB 2.0
Specification.
Port Test Modes
Contact ARC International for port test mode capabilities.
30.8.6.2.3 Managing Endpoints
The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a
uniquely addressable portion of a USB device that can source or sink data in a communications channel
between the host and the device. The endpoint address is specified by the combination of the endpoint
number and the endpoint direction.
The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a
device is always a control type data channel used for device discovery and enumeration. Other types of
endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific
behavior related to packet response and error handling. More detail on endpoint operation can be found in
the USB 2.0 specification.
The ARC USB-HS OTG High-Speed USB On-The-Go device controller hardware supports up to the USB
2.0 maximum of 32 endpoint specified numbers. Each additional endpoint beyond the required endpoint
position adds additional hardware logic. The maximum number of endpoint numbers available to the DCD
is configured at hardware synthesis timer. After synthesis, the DCD can enable, disable and configure
endpoint type up to the maximum selected during synthesis.
Each endpoint direction is essentially independent and can be configured with differing behavior in each
direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1-OUT
to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device
operation. The only exception is that control endpoints must use both directions on a single endpoint
number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses
the pair of directions.
Each endpoint direction requires a queue head allocated in memory. If the maximum of 16 endpoint
numbers, one for each endpoint direction are being used by the device controller, then 32 queue heads are
required. The operation of an endpoint and use of queue heads are described later in this document.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
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