MCIMX27 Datasheet, PDF (1080/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

High-Speed USB On-The-Go (HS USB-OTG)
Bit
15:8
Description
Split Completion Mask (µFrame C-Mask). This field is ignored by the host
controller unless the EPS field indicates this device is a low- or full-speed device
and this queue head is in the periodic list. This field (along with the Active and
SplitX-state fields) is used to determine during which micro-frames the host
controller should execute a complete-split transaction. When the criteria for using
this field are met, a zero value in this field has undefined behavior. This field is
used by the host controller to match against the three low-order bits of the
FRINDEX register. If the FRINDEX register bits decode to a position where the
µFrame C- Mask field is a one, then this queue head is a candidate for transaction
execution. There may be more than one bit in this mask set.
7:0
Interrupt Schedule Mask (µFrame S-mask). This field is used for all endpoint
speeds. Software should set this field to a zero when the queue head is on the
asynchronous schedule. A non-zero value in this field indicates an interrupt
endpoint. The host controller uses the value of the three low-order bits of the
FRINDEX register as an index into a bit position in this bit vector. If the µFrame
S-mask field has a one at the indexed bit position then this queue head is a
candidate for transaction execution. If the EPS field indicates the endpoint is a
high-speed endpoint, then the transaction executed is determined by the
PID_Code field contained in the execution area. This field is also used to support
split transaction types: Interrupt (IN/OUT). This condition is true when this field is
non-zero and the EPS field indicates this is either a full- or low-speed device. A
zero value in this field, in combination with existing in the periodic frame list has
undefined results.
30.8.2.6.2 Transfer Overlay
The nine DWords in this area represent a transaction working space for the host controller. The general
operational model is that the host controller can detect whether the overlay area contains a description of
an active transfer. If it does not contain an active transfer, then it follows the Queue Head Horizontal Link
Pointer to the next queue head. The host controller will never follow the Next Transfer Queue Element or
Alternate Queue Element pointers unless it is actively attempting to advance the queue. For the duration
of the transfer, the host controller keeps the incremental status of the transfer in the overlay area. When the
transfer is complete, the results are written back to the original queue element.
The DWord3 of a Queue Head contains a pointer to the source qTD currently associated with the overlay.
The host controller uses this pointer to write back the overlay area into the source qTD after the transfer is
complete.
Table 30-56. Current qTD Link Pointer
Bit
Description
31:5 Current Element Transaction Descriptor Link Pointer. This field contains the
address Of the current transaction being processed in this queue and corresponds
to memory address signals [31:5], respectively.
4:0 Reserved (R). These bits are ignored by the host controller when using the value
as an address to write data. The actual value may vary depending on the usage.
30-98
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor