MCIMX27 Datasheet, PDF (1280/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Multi-Layer AHB Crossbar Switch (MAX)
36.4.4 MAX Register Descriptions
This section contains the detailed register descriptions for the MAX registers.
36.4.5 Master Priority Registers (MPR0–MPR2)
The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and
resides in each slave port.
The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO
(Read Only) bit has been set in the Slave General Purpose Control Register the Master Priority Register
can only be read from, attempts to write to it will have no effect on the MPR and result in an error response.
Additionally, no two available master ports may be programmed with the same priority level. Attempts to
program two or more available masters with the same priority level will result in an error response and the
MPR will not be updated.
0x1003_F000 (MPR0)
0x1003_F100 (MPR1)
0x1003_F200 (MPR2)
Access: Supervisor Read/Write
31 30 29 28 27 26
25
24
23
22
21
20
19
18
17
16
R0 0 0 0 0 0 0 0 0
MSTR_5
0
MSTR_4
W
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R0
MSTR_3
0
MSTR_2
0
MSTR_1
0
MSTR_0
W
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Table 36-4. Master Priority Register (MPR0–MPR2)
Table 36-5. Master Priority Register Field Descriptions
Field
Description
31–23
22–20
MSTR_5
19
18–16
MSTR_4
15
Reserved. They are read as zero and should be written with zero for upward compatibility.
Master 5 Priority. These bits set the arbitration priority for master port 5 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
Reserved. They are read as zero and should be written with zero for upward compatibility.
Master 4 Priority. These bits set the arbitration priority for master port 4 on the associated slave port.
These bits are initialized by hardware reset.
000 This master has the highest priority when accessing the slave port.
111 This master has the lowest priority when accessing the slave port.
Reserved. They are read as zero and should be written with zero for upward compatibility.
36-6
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor