MCIMX27 Datasheet, PDF (1499/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Synchronous Serial Interface (SSI)
Apart from the above basic modes of operation, SSI supports the following modes which require some
specific programming.
• I²S mode
• AC97 mode
— AC97 Fixed mode
— AC97 Variable mode
In (non-I²S) slave modes (external frame sync), the SSI programmed word length setting should be equal
to the word length setting of the master. In I²S slave mode, the SSI programmed word length setting can
be lesser than or equal to the word length setting of the I²S master (external CODEC).
In slave modes, the SSI programmed frame length setting (DC bits) can be less than or equal to the frame
length setting of the master (external CODEC).
The following sections provide detailed descriptions of the above modes.
42.1.2.1 Normal Mode
Normal mode is the simplest mode of the SSI. It is used to transfer data in one time slot per frame. A time
slot is a unit of data and the WL[3:0] bits define the number of bits in a time slot. In Continuous Clock
mode, a frame sync occurs at the beginning of each frame. The length of the frame is determined by the
following factors:
• The period of the Serial Bit Clock (DIV2, PSR, PM[7:0] bits for internal clock or the frequency of
the external clock on the STCK port)
• The number of bits per time slot (WL[3:0] bits)
• The number of time slots per frame (DC[4:0] bits)
If Normal mode is configured with more than one time slot per frame, data is transferred only in the first
time slot. No data is transferred in subsequent time slots. In Normal mode, DC[4:0] values corresponding
to more than a single time slot in a frame, only result in lengthening the frame. Data transfer only takes
place during the first time slot of the frame.
42.1.2.1.1 Normal Mode Transmit
The conditions for data transmission from the SSI in Normal mode are:
1. SSI enabled (SSIEN = 1)
2. Enable FIFO and configure Transmit and Receive Watermark if FIFO is used.
3. Write data to Transmit Data Register (STX)
4. Transmitter enabled (TE = 1)
5. Frame sync active (for continuous clock case)
6. Bit clock begins (for gated clock case)
When the above conditions occur in Normal mode, the next data word is transferred into the Transmit Shift
Register (TXSR) from the Transmit Data Register 0 (STX0), or from the Transmit FIFO 0 Register, if
transmit FIFO 0 is enabled. The new data word is transmitted immediately.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
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