MCIMX27 Datasheet, PDF (1344/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Digital Audio MUX (AUDMUX)
AUDMUX Boundary
PORTx
TFS_obe
TFS_in
TFS_out
RFS_obe
RFS_in
RFCSELx[3:0]
RFS_out
TFCSELy[3:0]
AUDMUX Boundary
PORTy
Pin Boundary
FS_obe
FS_out
FS_in
IOPAD
TxFS
RFCSELx[3:0]
TFSn_obe, TFSn_in, RFSn_obe,
RFSn_in and FSn_in to/from other ports
TFCSELy[3:0]
TCLK_obe
TCLK_in
TCLK_out
RCLK_obe
RCLK_in
RCLK_out
RFCSELx[3:0]
CLK_obe
CLK_out
CLK_in
IOPAD
TxCLK
RFCSELx[3:0]
TCLKn_obe, TCLKn_in, RCLKn_obe
RCLKn_in and CLKn_in to/from other ports
Figure 38-4. Frame Sync and Clock Routing when Peripheral Port is 4-Wire
38.6 Synchronous Mode (4-Wire Interface)
In Synchronous mode the port will have a 4-wire interface—that is, RXD,TXD,TxCLK,TxFS.The
Receive clock and the receive frame sync will be the same as Transmit clock (TxCLK) and Transmit frame
sync (TxFS), respectively.
38-6
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor