MCIMX27 Datasheet, PDF (1357/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Digital Audio MUX (AUDMUX)
Table 38-5. Peripheral Port Configuration Register Field Descriptions
Field
Description
31
TFSDIR
Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as output
or input.When set as input, the TFCSEL settings are ignored.When set as output, the TFCSEL settings
determine the source port of the Frame Sync.
0 TxFS is input pin.
1 TxFS is output.
30
TCLKDIR
Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as output or
input.When set as input, the TFCSEL settings are ignored.When set as output, the TFCSEL settings
determine the source port of the Clock.
0 TxClk is input pin.
1 TxClk is output.
29–26
TFCSEL
Transmit Frame Sync and Clock Select. Selects the source port from which FS_obe, FS_out, CLK_obe, and
CLK_out are sourced.
0xxx Selects TxFS and TxClk from port
1xxx Selects RxFS and RxClk from port
xxx Selection ignored if self-port number
110 Reserved
111 Reserved
25
RSFDIR
Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as output
or input.When set as input, the RFCSEL settings are ignored.When set as output, the RFCSEL settings
determine the source port of the Frame Sync.
0 RxFS is input pin.
1 RxFS is output.
24
RCLKDIR
Receive Clock Direction Control. This bit sets the direction of the Waxlike pin of the interface as output or
input.When set as input, the RFCSEL settings are ignored.When set as output, the RFCSEL settings
determine the source port of the Clock.
0 RxClk is input pin.
1 RxClk is output.
23–20
RFCSEL
Receive Frame Sync and Clock Select. Selects the source port from which RxFS and RxClk are sourced.
RxFS and RxClk can be sourced from TxFS and TxClk, respectively, from other ports.
0xxx Selects TxFS and TxClk from port
1xxx Selects RxFS and RxClk from port
000–101 Port 1–Port 6
110 Reserved
111 Reserved
19–16 Reserved
15–13
RXDSEL
Receive Data Select. selects the source port for the RxD data (TxD_in or RxD_in). RXDSEL is ignored if
INMEN is enabled.
xxx Port number for TxD_in or RxD_in, ignored if equal to self port number
110 Reserved
111 Reserved
12
SYN
Synchronous/Asynchronous Select. SYN controls whether the receive and transmit functions of the port
occur synchronously or asynchronously with respect to each other. When SYN is set, synchronous mode is
chosen and the transmit and receive sections use common clock and frame sync signals. That is, the port is
a 4-wire interface.When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync
signals are used for the transmit and receive sections; that is, the port is a 6-wire interface.
0 Asynchronous mode
1 Synchronous mode (default)
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
38-19