MCIMX27 Datasheet, PDF (1312/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Direct Memory Access Controller (DMAC)
Table 37-4. DMAC Register Summary (continued)
Name
0x1000_1090
(RSSR0)
–
0x1000_1450
(RSSR15)
0x1000_1094
(BLR0)
–
0x1000_1454
(BLR15))
0x1000_1098
(RTOR0)
–
0x1000_1458
(RTOR15))
0x1000_1098
(BUCR0)
–
0x1000_1458
(BUCR15))
0x1000_109C
(CCNR0)
–
0x1000_145C
(CCNR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R0 _{0 0 0 0 0 0 0 0 0}
W
0
RSS [5: 0]
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R0 0 0 0 0 0 0 0 0 0
W
BL [5: 0]
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R
EN CLK PSC
W
CNT [12: 0]
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R
BU_CNT [15: 0]
W
R0 0 0 0 0 0 0 0
CCNR[23:16]
W
R
CCNR [15: 0]
W
37.4.3 General Registers
37.4.3.1 DMA Control Register (DCR)
The DMA Control Register (DCR) controls the input of the system clock, enabling, disabling, and
resetting of the DMA module.
37-10
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor