MCIMX27 Datasheet, PDF (901/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Universal Asynchronous Receiver/Transmitters (UART)
Table 28-8. UART Control Register 2 Field Descriptions (continued)
Field
8
PREN
7
PROE
6
STPB
5
WS
4
RTSEN
3
ATEN
2
TXEN
1
RXEN
0
SRST
Description
Parity Enable. Enables/Disables the parity generator in the transmitter and parity checker in the
receiver. When PREN is asserted, the parity generator and checker are enabled, and disabled
when PREN is negated.
0 Disable parity generator and checker
1 Enable parity generator and checker
Parity Odd/Even. Controls the sense of the parity generator and checker. When PROE is high,
odd parity is generated and expected. When PROE is low, even parity is generated and
expected. PROE has no function if PREN is low.
0 Even parity
1 Odd parity
Stop. Controls the number of stop bits transmitted after a character. When STPB is high, 2 stop
bits are sent. When STPB is low, 1 stop bit is sent. STPB has no effect on the receiver, which
expects 1 or more stop bits.
0 1 stop bit transmitted
1 2 stop bits transmitted
Word Size. Controls the character length. When WS is high, the transmitter and receiver are in
8-bit mode. When WS is low, they are in 7-bit mode. The transmitter ignores bit 7 and the
receiver sets bit 7 to 0. WS can be changed in-between transmission (reception) of characters,
however not when a transmission (reception) is in progress, in which case the length of the
current character being transmitted (received) is unpredictable.
0 7-bit transmit and receive character length (not including START, STOP, or PARITY bits)
1 8-bit transmit and receive character length (not including START, STOP, or PARITY bits)
Request to Send Interrupt Enable. Controls the RTS edge sensitive interrupt. When RTSEN is
asserted and the programmed edge is detected on the ipp_uart_rts_b pin, the RTSF bit is
asserted.
0 Disable request to send interrupt
1 Enable request to send interrupt
Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM).
0 AGTIM interrupt is disabled.
1 AGTIM interrupt is enabled.
Transmitter Enable. Enables/Disables the transmitter. When TXEN is negated the transmitter is
disabled and idle. When the UARTEN and TXEN bits are set the transmitter is enabled. If TXEN
is negated in the middle of a transmission, the UART disables the transmitter immediately, and
starts marking 1s. The transmitter FIFO cannot be written when this bit is cleared.
0 Disable the transmitter
1 Enable the transmitter
Receiver Enable. Enables/Disables the receiver. When the receiver is enabled, if the RXD input
is already low, the receiver does not recognize BREAK characters, because it requires a valid
1-to-0 transition before it can accept any character.
0 Disable the receiver
1 Enable the receiver
Software Reset. Resets the transmitter and receiver state machines, all FIFOs, and all status
registers. Once the software writes 0 to SRST, the software reset remains active for 4 clock
cycles of CKIH before the hardware deasserts SRST. The software can only write 0 to SRST.
Writing 1 to SRST is ignored.
0 Reset the transmit and receive state machines, all FIFOs and all status registers
1 No reset
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
28-13