MCIMX27 Datasheet, PDF (1316/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Direct Memory Access Controller (DMAC)
0x1000_1010 (DRTOSR)
Access: User Read-Only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 37-9. DMA Request Time-Out Status Register (DRTOSR)
Table 37-9. DMA Request Time-Out Status Register Field Descriptions
Field
31–16
15–0
CH15–CH0
Description
Reserved. These bits are reserved and should read 0.
Channel 15 to 0. Indicates the request time-out status of each DMA channel.
0 No DMA request time-out
1 DMA request time-out
37.4.3.6 DMA Transfer Error Status Register (DSESR)
A DMA transfer error is set when DMA data transfer results in an error. When any bit is set in this register
and the corresponding bit in the interrupt mask register is cleared, a DMA Error Interrupt is asserted to the
interrupt controller (AITC). DSESR indicates the channel, if any, the detected transfer error during a DMA
burst. Clear each bit by writing 1 to it.
0x1000_1014 (DSESR)
Access: User Read-Only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 37-10. DMA Transfer Error Status Register (DSESR)
37-14
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor