MCIMX27 Datasheet, PDF (293/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

ARM9 Platform
AIPI #
1
1
2
2
2
2
2
2
2
2
Table 9-1. AIPI ARM9 Platform IP Bus Support
Module Slot(s)
0
1–31
0
1–17
18–26
27
28
29
30
31
Use
AIPI1 Configuration Registers
Off platform IP Bus module support
AIPI2 Configuration Registers
Off platform IP Bus module support
Reserved
On platform ETB Register Interface
On platform ETB RAM Interface
On platform ETB RAM Interface
On platform JAM Interface
On platform MAX Interface
Refer to the ARM9 Platform AIPI specification for more details on the operation of the AIPI.
9.2.7 PAHBMUX–Primary AHB Mux
The PAHBMUX module is responsible for address decoding for the primary AHB module selects. In
addition, the PAHBMUX module will perform the primary AHB read data muxing, the primary AHB
watchdog, and other miscellaneous functions.
Refer to the ARM9 Platform AHBMUX design specification for more detail.
9.2.8 ROMPATCH
The ROMPATCH will sit on the ARM926EJ-S I-AHB and D-AHB interfaces which are connected to
MAX Master Ports 0 and 1. This location will allow for patching of both internal and external memory
addresses on both ARM926EJ-S processor buses. The registers of the ROMPATCH will be programmed
via the Primary AHB. The ROMPATCH can be used to patch source code or data tables. The ROMPATCH
supports 32 patches.
9.2.8.1 External Boot
An external boot feature exists in the ROMPATCH module which allows patching of the reset vector fetch
(address = 32’h0000_0000) if the boot_int signal is negated. This mechanism will cause the ARM926EJ-S
to, in effect, fetch the reset vector from the address indicated by the ext_boot_addr[31:2] inputs.
Refer to the ARM9 Platform ROMPATCH design specification for more details.
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
9-9