MCIMX27 Datasheet, PDF (392/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

External Memory Interface (EMI)
Table 15-2. External Memory Interface I/O MUX Description (continued)
SDRAMC MDDRC
MEMORY Controller Outputs
PCMCIA
WEIM
NFC
EMI Output
IC Pin
Name
—
IPP_DO_CARD_ADD WEIM_ADDR_OUT[21]
—
RESS_O[21]
IPP_DO_E M I
A21
_ADDR [21]
—
IPP_DO_CARD_ADD WEIM_ADDR_OUT[22]
—
RESS_O[22]
IPP_DO_E M I
A22
_ADDR [22]
—
IPP_DO_CARD_ADD WEIM_ADDR_OUT[23]
—
RESS_O[23]
IPP_DO_E M I
A23
_ADDR [23]
—
IPP_DO_CARD_ADD WEIM_ADDR_OUT[24]
—
RESS_O[24]
IPP_DO_E M I
A24
_ADDR [24]
—
IPP_DO_CARD_ADD WEIM_ADDR_OUT[25]
—
RESS_O[25]
IPP_DO_E M I
A25
_ADDR [25]
ESDCTL address bit M3IF_MA[10] has a dedicated pad MA10 (required due to PRECHARGE ALL during AUTO REFRESH
commands).
ESDCTL BANK address bits have dedicated PADS due to PRECHARGE BANK during PRECHARGE TIMER time-out
WEIM CRE signal is driven on A23 in MUXED MODE OPERATION.
M3IF_MA[10]
—
—
—
IPP_DO_E M I
MA10
_MA10
M3IF_BA[0]
IPP_DO_CARD_CE_
—
B[2]
—
IPP_DO_SDBA[1:0] SDBA0
M3IF_BA[1]
IPP_DO_CARD_CE_
—
—
B[1]
SDBA1
Since SDBA PADS are shared between SDR/DDR SDRAM BANK ADDRESS and PCMCIA CE‘, ESDCTL PRECHARGE TIMER
cannot be used. During precharge timer, after selected inactivity period of time expires, ESDCTL issue a PRECHARGE command
to a specific bank during OFF LINE period. It means that PRECHARGE command can be issued during the time when EMI BUS
is not possessed by ESDCTL.
SDRAM/MDDR Dedicated Data Pads
M3IF_WR_DATA[0]
—
—
—
IPP_DO_EMII_DATA SD0
[0]
M3IF_RD_DATA[0]
IPP_IND_EMII_DATA
_IN [0]
M3IF_WR_DATA[1]
—
—
—
IPP_DO_EMII_DATA SD1
[1]
M3IF_RD_DATA[1]
IPP_IND_EMII_DATA
_IN [1]
M3IF_WR_DATA[2]
—
—
—
IPP_DO_EMII_DATA SD2
[2]
M3IF_RD_DATA[2]
IPP_IND_EMII_DATA
_IN [2]
15-12
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor