MCIMX27 Datasheet, PDF (1500/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Synchronous Serial Interface (SSI)
If transmit FIFO 0 is not enabled and the transmit data register empty (TDE0) bit is set, transmit interrupt
0 occurs if the transmit interrupt enable (TIE) and TDE0_EN bits are set.
The Transmit FIFO Empty 0 (TFE0) bit is set if the Transmit FIFO 0 reaches the selected threshold. If
transmit FIFO 0 is enabled and the Transmit FIFO Empty (TFE0) bit is set, transmit interrupt 0 occurs if
the transmit interrupt enable (TIE) and TFE0_EN bits are set. If transmit FIFO 0 is enabled and filled with
data, 8 data words can be transferred before the core must write new data to the STX0 register.
The STXD port is disabled except during the data transmission period. For a continuous clock, the optional
frame sync output and clock outputs are not disabled, even if both receiver and transmitter are disabled.
42.1.2.1.2 Normal Mode Receive
The conditions for data reception from the SSI are:
1. SSI enabled (SSIEN = 1)
2. Receiver enabled (RE = 1)
3. Frame sync active (for continuous clock case)
4. Bit clock begins (for gated clock case)
With the above conditions in Normal mode with a continuous clock, each time the frame sync signal is
generated (or detected) a data word is clocked in. With the above conditions and a gated clock, each time
the clock begins, a data word is clocked in.
If receive FIFO 0 is not enabled, the received data word is transferred from the Receive Shift Register
(RXSR) to the Receive Data Register 0 (SRX0), the Receive Data Ready 0 (RDR0) flag is set. Receive
Interrupt 0 occurs if RIE and RDR0_EN bits are set.
If receive FIFO 0 is enabled, the received data word is transferred to the Receive FIFO 0. The Receive
FIFO Full 0 (RFF0) flag is set if the Receive Data Register (SRX0) is full and Receive FIFO 0 reaches the
selected threshold. Receive Interrupt 0 occurs if Receive Interrupt Enable (RIE) and RFF0_EN bits are set.
The core program has to read the data from the Receive Data Register 0 (SRX0) before a new data word
is transferred from the Receive Shift Register (RXSR), otherwise the Receive Overrun Error 0 (ROE0) bit
is set. If receive FIFO 0 is enabled, the Receive Overrun Error 0 (ROE0) bit is set when the Receive FIFO
0 data level reaches the selected threshold and a new data word is ready to be transferred to the Receive
FIFO 0.
Figure 42-2 shows transmitter and receiver timing for an 8-bit word in the first time slot in Normal mode,
continuous clock with a late word length frame sync. The Tx Data register is loaded with the data to be
transmitted. On arrival of the frame sync, this data is transferred to the Transmit Shift Register and
transmitted on the STXD output. Simultaneously, the Receive Shift Register shifts in the received data
available on the SRXD input and at the end of the time slot, this data is transferred to the Rx Data Register.
42-6
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor