MCIMX27 Datasheet, PDF (1535/1650 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Synchronous Serial Interface (SSI)
SSI Interrupt Sources
SSI Receive Data with Exception Status 0/1
SSI Receive Data 0/1
SSI Receive Last Time Slot
SSI Transmit Data with Exception Status 0/1
SSI Transmit Data 0/1
SSI Transmit Last Time Slot
SSI AC97 Command Address Updated
SSI AC97 Command Data Updated
SSI AC97 Receive Tag Updated
SSI Receive Frame Sync
Figure 42-26. SSI Interrupts
NOTE
SSI Status flags are updated when SSI is enabled.
Refer to Section 42.4.3, “Receive Interrupt Enable Bit Description” and
Section 42.4.4, “Transmit Interrupt Enable Bit Description” for interrupt
source mapping.
All the flags in the SISR are updated after the first bit of the next SSI word
has completed transmission or reception. Some status bits (ROE0/1 and
TUE0/1) are cleared by reading the SISR followed by a read or write to
either the SRX0/1 or STX0/1 registers.
See Figure 42-27 for an illustration of valid bits in SSI Interrupt Register and Table 42-13 for descriptions
of the bit fields in the register.
0x1001_1014 (SISR)
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
0
0
0
CMD
AU
CMD
DU
RXT
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS RFS TLS RLS RFF1 RFF0 TFE1 TFE0
W
Reset 0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
Figure 42-27. SSI Interrupt Status Register
MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2
Freescale Semiconductor
42-41