MC68HC16Z1CAG16 Datasheet, PDF (93/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
4.9 Instruction Format
CPU16 instructions consist of an 8-bit opcode that can be preceded by an 8-bit prebyte
and followed by one or more operands.
Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone.
Page 1, 2, and 3 opcodes are pointed to by a prebyte code on page 0. The prebytes
are $17 (page 1), $27 (page 2), and $37 (page 3).
Operands can be four bits, eight bits or sixteen bits in length. Since the CPU16 fetches
16-bit instruction words from even-byte boundaries, each instruction must contain an
even number of bytes.
Operands are organized as bytes, words, or a combination of bytes and words. Oper-
ands of four bits are either zero-extended to eight bits, or packed two to a byte. The
largest instructions are six bytes in length. Size, order, and function of operands are
evaluated when an instruction is decoded.
A page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions
that use 8-bit indexed, immediate, and relative addressing modes have this form.
Code written with these instructions is very compact.
Figure 4-4 shows basic CPU16 instruction formats.
M68HC16 Z SERIES
USER’S MANUAL
CENTRAL PROCESSING UNIT
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