MC68HC16Z1CAG16 Datasheet, PDF (445/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table D-44 PAMOD and PEDGE Effects
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Effect
PAI falling edge increments counter
PAI rising edge increments counter
Zero on PAI inhibits counting
One on PAI inhibits counting
PCLKS — PCLK Pin State (Read Only)
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
Table D-45 shows the PACLK[1:0] bit field effects.
Table D-45 PACLK[1:0] Effects
PACLK[1:0]
00
01
10
11
Pulse Accumulator Clock Selected
System clock divided by 512
Same clock used to increment TCNT
TOF flag from TCNT
External clock, PCLK
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumula-
tion.
D.8.8 Input Capture Registers 1–3
TIC[1:3] — Input Capture Registers 1–3
$YFF90E – $YFF912
The input capture registers are 16-bit read-only registers used to latch the value of
TCNT when a specified transition is detected on the corresponding input capture pin.
They are reset to $FFFF.
D.8.9 Output Compare Registers 1–4
TOC[1:4] — Output Compare Registers 1–4
$YFF914 – $YFF91A
The output compare registers are 16-bit read/write registers which can be used as out-
put waveform controls or as elapsed time indicators. For output compare functions,
they are written to a desired match value and compared against TCNT to control spec-
ified pin actions. They are reset to $FFFF.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
D-71