MC68HC16Z1CAG16 Datasheet, PDF (404/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
D.5.1 ADC Module Configuration Register
ADCMCR — ADC Module Configuration Register
15
14
13
12
STOP
FRZ
RESET:
1
0
0
NOT USED
8
7
6
SUPV
1
NOT USED
$YFF700
0
ADCMCR controls ADC operation during low-power stop mode, background debug
mode, and freeze mode.
STOP — Low-Power Stop Mode Enable
0 = Normal operation
1 = Low-power operation
STOP places the ADC in low-power state. Setting STOP aborts any conversion in
progress. STOP is set to logic level one during reset, and may be cleared to logic level
zero by the CPU16. Clearing STOP enables normal ADC operation. However, be-
cause analog circuitry bias current has been turned off, there is a period of recovery
before output stabilization.
FRZ[1:0] — Freeze Assertion Response
The FRZ field determines ADC response to assertion of the FREEZE signal when the
device is placed in background debug mode. Refer to Table D-25.
Table D-25 Freeze Encoding
FRZ[1:0]
00
01
10
11
Response
Ignore FREEZE, continue conversions
Reserved
Finish conversion in process, then freeze
Freeze immediately
SUPV — Supervisor/Unrestricted
This bit has no effect because the CPU16 always operates in supervisor mode.
D.5.2 ADC Test Register
ADCTEST — ADC Test Register
Used for factory test only.
$YFF702
D.5.3 Port ADA Data Register
PORTADA — Port ADA Data Register
15
14
13
12
11
10
9
8
NOT USED
RESET:
$YFF706
7
6
5
4
3
2
1
0
PADA7 PADA6 PADA5 PADA4 PADA3 PADA2 PADA1 PADA0
REFLECTS STATE OF THE INPUT PINS
Port ADA is an input port that shares pins with the A/D converter inputs.
D-30
REGISTER SUMMARY
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M68HC16 Z SERIES
USER’S MANUAL