MC68HC16Z1CAG16 Datasheet, PDF (449/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
FOC[5:1] — Force Output Compare
FOC[5:1] correspond to OC[5:1].
0 = Has no effect.
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is
not set. FOC[5:1] correspond to OC[5:1].
FPWMA/B — Force PWM Value
0 = PWM pin A/B is used for PWM functions; normal operation.
1 = PWM pin A/B is used for discrete output. The value of the F1A/B bit will be driv-
en out on the PWMA/B pin. This is true for PWMA regardless of the state of the
PPROUT bit.
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PWMA.
1 = Clock selected by PPR[2:0] is driven out PWMA pin.
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps or PCLK to be PWMCNT input. Refer to
Table D-49.
Table D-49 PPR[2:0] Field
PPR[2:0]
000
001
010
011
100
101
110
111
System Clock Divide-By Factor
2
4
8
16
32
64
128
PCLK
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
Table D-50 shows a range of PWM output frequencies using 16.78 MHz, 20.97 MHz,
and 25.17 MHz system clocks.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
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